Target tracking in high-performance aircraft involves the use of a pre-processor which analyzes the movement of a pilot-selected target across the video image seen by the pilot, and provides tracking information to a tracking device which centers the field of view of the sensor about the target.
Accurately recognizing and locating selected targets of different size, shape and intensity against complex backgrounds in successive fields of the video scan is no easy task. To provide reliable tracking, the image needs to be examined by several preprocessing algorithms which may be different for different kinds of targets. Tracking information is then derived from a comparison of the results of the algorithms used. Typically, such algorithms include geometric (for large targets) and intensity (for small targets) centroids, and convolution-based algorithms such as Sobel edge detection, brightness feature match correlation (BFMA) or Sum of Products, difference squared (.DELTA..sup.2), and sequential similarity detection (SSDA) algorithms.
The pre-processing task is further complicated by the fact that during abrupt maneuvers of the aircraft, the target aspect changes rapidly as a result of image rotation.
A significant factor in the design of tracking pre-processors is the fact that all calculations have to be completed in no more than 15 ms so that a new set of results can be generated for each field of the 60 Hz video scan. In the prior art, it was necessary to provide a separate pre-processor for each algorithm to allow simultaneous computation of all the results within the available time interval--an undesirable situation from the point of view of cost, weight, size and power.
Prior art in this field includes: U.S. Pat. No. 4,363,104 to Nussmeier, which deals with a process for creating multiple images for simultaneous processing; U.S. Pat. No. 4,433,438 to Couturier, which discloses a circuit for processing the Sobel square root edge extraction algorithm; U.S. Pat. No. 4,464,789 to Sternberg in which successive images are analyzed for motion therebetween; U.S. Pat. No. 4,484,346 to Sternberg et al which ties multiple chips together but basically performs only a series of 3.times.3 convolutions; U.S. Pat. No. 4,484,349 to McCubbrey in which a plurality of pipelines simultaneously operate on adjacent segments of an image matrix; U.S. Pat. No. 4,499,597 to Alves which describes a centroid calculation; U.S. Pat. No. 4,750,144 to Wilcox which shows a circuit for convolution computations; and U.S. Pat. No. 4,790,026 to Gennery et al which discusses a modular pipelined image processor.